The schematic block diagram of an image sensor 1 is shown in FIG. 1. The image sensor 1 may be an integrated visible CMOS imager or a readout integrated circuit (ROIC) for infrared (IR) or ultraviolet (UV) detectors. The particular image sensor 1 shown in FIG. 1 is an integrated visible CMOS imager that comprises a two-dimensional (2-D) pixel array 10, one-dimensional array of column sample and hold circuits 20, and analog horizontal bus driver and multiplexer circuits 30. The row decoder and logic circuit arrays 40 and the column decoder and logic circuit arrays 50 access the pixels 12 in the pixel array 10 for reading. If the image sensor 1 is an ROIC, a two-dimensional pixel readout/multiplexer takes the place of a 2-D pixel array, because the sensing elements are usually on a separate chip from the electronics described here, but the rest of the circuits remain the same. The current disclosure relates primarily to the analog horizontal bus driver and multiplexer.
FIG. 2 shows the schematic for the CMOS imager/ROIC architecture with a source-follower per detector architecture. Individual pixels 12 of the 2-D pixel array consists of a photodiode 15 implemented with a reverse-biased p-n junction that is integrated on the same chip for a CMOS imager or hybridized to the ROIC; and a source follower is comprised of transistors Min 14 (SF input FET), Msel 16 (select FET), and Mrst 18 (reset FET).
The image sensor 1 operates in a column-parallel fashion (i.e., a row at a time). To begin exposure, the pixels 12 in a given row are reset by momentarily pulsing the line RST 11 high. Following exposure, the pixels 12 are readout in a row-at-a-time fashion. For readout, a row is selected by momentarily pulsing the line SEL 13 high. The source follower output from each pixel belonging to the row is available over the column buses 17. The column-parallel outputs are sampled by an array of bottom-of-column capacitors (CS) 21 by pulsing the line SHS 23 high. The pixels 12 are then reset by momentarily pulsing the line RST 11 high, and the resultant outputs are again sampled on another array of bottom-of-the-column capacitors (CR) 25 by pulsing the line SHR 27 high. The difference of the sampled voltages in each column 17 is the signal from each pixel 12, and is proportional to the charge accumulation on each photodiode 15.
The sampled voltages in each column 17 (on the capacitors 21 (CS) and 25 (CR)) are scanned out by using an analog horizontal bus driver/multiplexer circuit. FIG. 3 shows a schematic of two analog bus driver/multiplexer circuits 31 and 33. The capacitors 21 (Cs) and 25 (CR) in each column 17 are buffered by the analog horizontal bus driver circuits 31 and 33. The output of the analog horizontal bus driver circuits 31 and 33 in each column 17 drives the capacitance of the horizontal buses 35 and 37 which feed, respectively, output buffer amplifiers 38 and 39. The analog bus driver circuits 31 occur in pairs in order to differentially readout sampled voltages from bottom-of-column capacitors 21 (CS) and 25 (CR) in each column 17.
For a large format array, the analog horizontal bus driver and multiplexer circuit 30 drives a large capacitance, and needs to have excellent linearity, large signal swing, high speed of operation, and near-ideal gain.
Accordingly, the two-dimensional pixel array is readout as follows in a typical CMOS imager or a focal-plane readout integrated circuit (IC) 1. First, the outputs of a row of pixels 12 are sampled in parallel at the bottom of the column 17. The sampled values are then scanned out using electronic amplifiers 38 and 39. The speed of column scanning determines the readout rate. FIGS. 4 and 5 show the two most common column amplifier schemes for reading out the pixel values.
Source-Follower Signal Chain
FIG. 4 shows the schematic diagram of a conventional column source-follower signal chain. See R. H. Nixon, S. E. Kemeny, B. Pain, C. O. Staller, and E. R. Fossum, “256×256 CMOS active pixel sensor camera-on-a-chip,” IEEE Journal of Solid-State Circuits, vol. 31, pp. 2046-2050, December 1996, the disclosure of which is incorporated by reference herein for all purposes allowed by law and regulation.
As shown in FIG. 4, the pixel values sampled at the bottom of the column 17 are stored on column capacitors 111 (Cs). The reference capacitors (CR), their associated FETs, and a horizontal bus are omitted for the sake of simplifying the diagram and discussion. The sampled values are then scanned using a switched source-follower circuit 100 consisting of Msf as the input FET 105, Msel, as the selection switch FET 110 controlled by a column-decoded digital signal, and Mld as the load FET 115. While Msf and Msel are present in each column cell buffering the sample-and-hold capacitor 21 (Cs), there is only one load FET 115 (Mld), since only one column is activated at a time during the scanning in order to provide a signal to the horizontal bus 112.
The same structure is duplicated in order to readout the signal in a differential fashion using the sample and hold capacitors 25 (CR) (not shown in FIG. 4 but shown in FIGS. 2 and 3). In that case, the bottom-of-the-column sample-and-hold capacitors 25 and 21 (CR and CS) consist of a pixel reference level (VR) and a signal level (VS) corresponding to pixel potentials before and after photo-generated charges have been accumulated.
The output of a particular column n Vout(n) depends on the voltage drops across the FETs 105 (Msf) and 110 (Msel). In turn, they depend on the bias current Ibias, and the width and length ratio (W/L) of the respective FETs. For a given bias current, Ibias, the output voltage for column of index n is given by:
                                                                                          V                  out                                ⁡                                  (                  n                  )                                            ≡                              V                out                                      =                                          V                Cs                            +                              V                to                            +                                                                    2                    ⁢                                                                                  ⁢                                          I                      bias                                                                            β                    sf                                                              +                              Δ                ⁢                                                                  ⁢                                                      V                    drop                                    ⁡                                      (                                          V                      Cs                                        )                                                                                ;                ⁢                                  ⁢                              β            sf                    =                      μ            ·                          C              ox                        ·                                          [                                  W                  L                                ]                            sf                                                          [        1        ]            where the index is dropped for simplicity, VCs is the sampled voltage on the capacitor Cs, Vto is the threshold voltage of Msf, W/L is the transistor width to length ratio, ΔVdrop is the voltage drop across the drain and source of the switch FET Msel, βsf is the transconductance factor for Msf, μ is the mobility of carriers in the channel, and Cox is the oxide capacitance per unit area. Since Ibias flows through the select FET 110 (Msel) as well, (assuming that FET 110 (Msel) is biased in the linear region of FET operation), ΔVdrop can be computed from:
                              I          bias                =                              β            sel                    ·                      [                                                            (                                                            V                      out                                        -                                          V                      tsel                                                        )                                ·                                  (                                                            V                      out                                        -                                          V                      s                                                        )                                            -                                                1                  2                                ·                                                      (                                                                  V                        out                                            -                                              V                        s                                                              )                                    2                                                      ]                                              [        2        ]            where Vs is the voltage at the source of FET 105 (Msf) and is given by:
                              V          s                =                                            V              Cs                        +                          V              to                        +                                                            2                  ⁢                                                                          ⁢                                      I                    bias                                                                    β                  sf                                                              =                                    V              out                        -                          Δ              ⁢                                                          ⁢                                                V                  drop                                ⁡                                  (                                      V                    Cs                                    )                                                                                        [        3        ]            
Assuming that the effective threshold voltage Vtsel changes linearly with VSB the source-to-body voltage (as shown in Equation 4—clearly an approximation introduced to simplify analysis), Equation 2 can be solved to yield (with γ being the FET body coefficient):
                                          V            out                    =                                    1                              1                -                γ                                      ·                          [                                                V                  to                                -                                                      γ                    ⁢                                                                                  ⁢                                          V                      s                                                        2                                +                                                                            V                      to                      2                                        +                                                                                            (                                                      1                            -                                                          γ                              2                                                                                )                                                2                                            ⁢                                              V                        s                        2                                                              -                                                                  (                                                  γ                          +                          2                                                )                                            ·                                              V                        s                                            ·                                              V                        to                                                              +                                                                  2                        ·                                                  (                                                      1                            -                            γ                                                    )                                                ·                                                  I                          bias                                                                                            β                        sel                                                                                                        ]                                      ⁢                                  ⁢                              V            tsel                    =                                    V              to                        +                                          γ                ⁢                                                                  ⁢                                  V                  SB                                            2                                                          [        4        ]            
The response time is determined by the time required to charge the horizontal bus parasitic (CB) and load capacitance (CL), and depends on the bias current (Ibias) and the transconductance of the FET 105 (Msf) and the channel resistance of the select FET 110 (Msel). By adding the slewing and the settling time together (assuming single pole response), the dependence Ibias on the column readout time (Δtread) is given by:
                                          I            bias                    =                                    I              R                        +                                                            I                  S                                2                            ⁡                              [                                  1                  +                                                            1                      +                                              4                        ⁢                                                                                                  ⁢                                                                              I                            R                                                                                I                            S                                                                                                                                              ]                                                    ⁢                                  ⁢                                            I              R                        =                                                                                (                                                                  C                        L                                            +                                              C                        B                                                              )                                    ·                  Δ                                ⁢                                                                  ⁢                V                                                              ζ                  ·                  Δ                                ⁢                                                                  ⁢                                  t                  read                                                              ;                                          ⁢                                    I              S                        =                                                                                (                                                                  C                        L                                            +                                              C                        B                                                              )                                    2                                ·                χ                                            2                ⁢                                                                  ⁢                                                      β                    eff                                    ·                  Δ                                ⁢                                                                  ⁢                                  t                  read                  2                                                              ;                ⁢                                  ⁢                                  ⁢                              C            B                    =                                    N              col                        ·                          (                                                                    W                    sel                                    ·                                      C                    edge                                                  +                                  C                  par                                            )                                      ⁢                                  ⁢                              β            eff                    =                                                    β                sel                            ⁡                              (                                                      β                    sf                                                                              β                      sf                                        +                                          β                      sel                                                                      )                                      2                                              [        5        ]            where CL is the fixed load capacitance, and CB is the bus capacitance, with Cedge being the parasitic capacitance along the edge of the select FET 110 (Msel), and Cpar is the parasitic capacitance independent of the select FET 110 (Msel), Ncol is the number of columns, ξ is the ratio of current between the output transient current and the bias current, Wsel is the width of the select capacitor 110 (Msel), and χ is the setting factor, that is, the ratio of the settling time to the time constant (˜7 for 0.1% accuracy).
As shown in Equations 4 and 5, both output voltage and readout time are strong functions of the bias current, as well as the size of the column FETs 105 and 110 (Msf and Msel). Equation 4 also shows that the transfer function is extremely non-linear, the non-linearity resulting from the ohmic voltage drop across the FET switch 110 (Msel). This voltage drops also causes a drastic reduction in the signal swing. Finally, except in a handful of situations, for a given operating speed, an increase in the W/L ratio of the switch FET 110 (Msel) produces undesirable results: increase in both the required bias current and non-linearity, and reduction in the output voltage swing.
OPAMP Signal Chain
FIG. 5 shows a representative schematic of an opamp signal chain 120. The sample-and-hold capacitors 121 and 125 (Cs and CR) are connected to the horizontal buses 135 and 137 through selection switches 128 (Msel). Unlike the source-follower signal chain described above, the horizontal buses 135 and 137 are held at a virtual ground via opamp feedback from the operational amplifier 131, and no dc current flows through the selection switches 128. Once a particular set of column capacitors are selected, the charge in the capacitor is transferred to the corresponding feedback capacitor 136 (Cf) through the feedback action, producing an output:
                              V          out                =                                            V              out              +                        -                          V              out              -                                =                                                    C                s                                            C                f                                      ·                                          C                x                                            C                g                                      ·                          [                                                V                  R                                -                                  V                  S                                            ]                                                          [        6        ]            where Vout+(−) are the outputs from the two sides of the differential signal chain, and VR and VS are the sampled pixel outputs corresponding to the reset level and the signal level respectively as discussed above in connection with FIG. 2. A big advantage of the opamp signal chain is its ability to provide accurate voltage gain, as shown in Equation 6, the voltage gain being defined as two capacitor ratios that are easy to implement using standard Very Large Scale Integration (VLSI) layout techniques.
Since no dc current flows through the horizontal buses 135 and 137, the resistive drop issues are no longer of concern. However, the bus capacitance (CB) significantly impacts the setting time through the Miller effect, causing a drastic increase in the opamp bias current with an increase CB. The Miller effect refers to the multiplication of the capacitance between input and output of an amplifier by a factor of (1−Av), in which Av is the open-loop voltage gain of the operational amplifier. The capacitance will charge and discharge with a current multiplied by (1−Av).
Assuming that a single stage design is employed to implement the opamp, the dependence of the required bias current (Ibias) to the column readout time (Δtread) is given by:
                                          I            bias                    =                      2            ·                          {                                                I                  R                                +                                                                            I                      S                                        2                                    ⁡                                      [                                          1                      +                                                                        1                          +                                                      4                            ⁢                                                                                                                  ⁢                                                                                          I                                R                                                                                            I                                S                                                                                                                                                                          ]                                                              }                                      ⁢                                  ⁢                                            I              R                        =                                                                                (                                                                  C                        L                                            +                                              C                        B                                                              )                                    ·                  Δ                                ⁢                                                                  ⁢                V                                                              ζ                  ·                  Δ                                ⁢                                                                  ⁢                                  t                  read                                                              ;                                          ⁢                                    I              S                        =                                                            C                  x                  2                                ·                χ                                            2                ⁢                                                                  ⁢                                                      β                    op                                    ·                  Δ                                ⁢                                                                  ⁢                                  t                  read                  2                                                              ;                ⁢                                  ⁢                              C            B                    =                                    N              col                        ·                          (                                                                    W                    sel                                    ·                                      C                    edge                                                  +                                  C                  par                                            )                                      ⁢                                  ⁢                                            β              op                        =                          μ              ⁢                                                          ⁢                                                                    C                    ox                                    ⁡                                      (                                          W                      L                                        )                                                  op                                              ;                ⁢                                  ⁢                                  ⁢                              C            x                    =                                                    [                                                      C                    L                                    +                                                                                    C                        f                                            ·                                              (                                                                              C                            B                                                    +                                                      C                            s                                                                          )                                                                                                            C                        f                                            +                                              C                        B                                            +                                              C                        s                                                                                            ]                            ·                              [                                                                            C                      f                                        +                                          C                      B                                        +                                          C                      s                                                                            C                    f                                                  ]                                      =                                          C                y                            ·                                                                    C                    f                                    +                                      C                    B                                    +                                      C                    s                                                                    C                  f                                                                                        [        7        ]            
It can be seen from the above equation that the opamp signal chain does not suffer from any ohmic drop problems, but the bias current required for a given readout time increases rapidly with CB (the horizontal bus parasitic capacitance) due to the Miller effect (captured in the expression for Cx). Note that a two-stage design will have qualitatively similar response.
Design Problems
Both signal chain implementations face serious design problems: the opamp chain suffering from the Miller effect from the horizontal bus capacitance, and the source-follower from Msel sizing issues.
For the source-follower signal chain described in connection with FIG. 4, the problem is as follows. FIG. 6 shows that the transfer function of the column source-follower driving the horizontal bus has marked non-linearity. Reduction of non-linearity requires operation with reduced bias current and increased W/L ratio of the selection switch FET 110 (Msel). However, even for W/L as large as 40/1, the transfer function continues to exhibit non-linearity at low input voltage levels.
Increasing the Msel size (thus increasing the W/L ratio) results in a number of undesirable effects. Increasing the width of Msel increases the bus capacitance, because of the increase in the source capacitance of Msel connected to the horizontal bus. For a fixed bias current, the readout rate and hence the frame rate falls rapidly, the rapid fall resulting from the fact that settling time is inversely proportional to the trans-conductance (gm) of a FET (Msf in this case), and the transcondutance is proportional to the square root of the product of Ibias and W/L ratio, as shown in Equation 8.
                              g          m                ∝                                            I              bias                        ·                          W              L                                                          [        8        ]            
FIG. 7 shows the simulated results of the effect of W/L ratio of Msel on the frame rate and the output voltage swing of the source-follower. It shows that for small Msel widths (Wsel in μm), the frame rate is high—reaching a maximum around Wsel˜2 μm. As Wsel is increased, the frame rate falls rapidly, due to (as explained above) an increase in the horizontal bus capacitance. On the other hand, the output voltage swing (and resultant non-linearity) shows an exactly opposite behavior: voltage swing is unacceptably small for small Wsel.
FIG. 8 demonstrates this contradictory behavior even more clearly—both voltage swing and gain reducing rapidly as the frame-rate is increased. The presence of the inverse relationship between frame rate and voltage swing (and gain) makes it very difficult to find a suitable operating point for this kind of source-follower circuit, especially as the number of imager pixels is increased.
Therefore, for a conventional source-follower driving the horizontal bus, the voltage drop across Msel precludes high speed operation with sufficient voltage swing and linearity.
Although ohmic drops are not problems for the opamp signal chain, its main problem is a rapid reduction in frame rate for a fixed bias current, as Wsel size is increased. Since no dc current flows through Msel (shown as switches 128 in FIG. 2), the output voltage swing and the transfer gain remains unaffected by Msel size. Therefore, the opamp signal chain can be designed with small Wsel to minimize the bus capacitance, and increase frame rate, without affecting the output voltage swing or transfer gain.
However, an opamp signal chain has its limitations as well. First, the opamp signal chain suffers from a larger increase due to the Miller Effect from the horizontal bus capacitance. This effect appears as a capacitance multiplier (see Equation 7). Therefore, for the value of Wsel, the effective bus capacitance seen by the opamp is larger than that seen by a source-follower circuit.
Secondly, an opamp based signal chain may provide increased pixel fixed pattern noise, if the capacitors on the two sides of the opamp (shown in FIG. 5) are not accurately matched. Thirdly, compared with that in a source follower circuit, noise in the opamp signal chain also increases as a result of the Miller Effect.
Thus, the problems can be summarized as follows.
1. For a source-follower signal chain, the ohmic drop in Msel causes unacceptably small voltage swing, large non-linearity, and reduced small signal gain at a given bias current as the frame-rate is increased, especially for large format arrays.
2. For an opamp signal chain, the output noise rises rapidly while frame rate drops rapidly (at a fixed bias current) with increasing the array format due to a rapid increase in the effective horizontal bus capacitance caused by the Miller effect.